RTL → GDS in one conversation
Natural language to verified GDS. Kepler orchestrates the entire ASIC toolchain so you can focus on design, not tools.
Live Demo
Kepler takes a 4-bit counter from natural language to foundry-ready GDS.
The Pipeline
Every design passes through rigorous checks. Each gate must be GREEN before advancing.
NL → Verilog-2001. Latch-free, explicit resets.
0 errors, 0 warnings, 0 implicit wires.
Reset, boundaries, FSM, random ≥128. Coverage ≥95%.
BMC depth≥20, prove <200FF. No X after reset.
Scan chain, ATPG ≥97%.
Liberty-based mapping for Sky130/GF180.
Setup/hold sanity check.
Floorplan → Place → CTS → Route. 45% util.
Skew <50ps. Balanced buffer insertion.
Zero foundry violations.
Physical matches logical.
Oxide protection. Auto-diode.
TT · SS · FF on SPEF netlist.
IR <5% VDD. Foundry-ready GDSII.
14
Sign-off Gates
3
STA Corners
95%+
Coverage
0
Violations
What sets it apart
Traditional EDA requires weeks of TCL scripting and manual iteration. Kepler replaces that with an AI orchestrator that understands intent, fixes errors autonomously, and never claims success without proof.
Describe your design in plain English. Kepler generates Verilog-2001 that's immediately lint-clean — no implicit wires, no latches. Every FF gets explicit reset.
Timing violation, DRC error, LVS mismatch — Kepler diagnoses root cause, applies targeted fix, re-runs verification. Loop until all gates pass.
Post-route SPEF-annotated STA across TT, SS, FF corners. Setup/hold fixed with buffer insertion and gate sizing.
Sky130 (130nm) and GF180MCU (180nm). No licenses, no seat fees. Entire toolchain is FOSS.
Every gate backed by tool output — raw logs alongside the final GDS. No summaries, no estimates.
TinyTapeout tt_um_* naming, info.yaml, I/O ports, CI-grade DRC/LVS. Foundry-spec GDSII for custom runs.
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